1. Field of the Invention
The invention relates generally to phase-locked loop (PLL) circuitry, and more particularly to systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in PLLs.
2. Related Art
A PLL is a control circuit that generates and output signal which has a fixed relationship to a reference signal that is input to the PLL. The PLL adjusts an internally generated signal so that this signal matches both the frequency and the phase of the reference signal.
PLLs are widely used in radio, telecommunication, computer and other fields of electronics to generate signals having stable frequencies and known phases with respect to a reference signal. PLLs may be used, for instance, in computer systems to generate clock signals for distribution to digital logic circuits so that these circuits can operate in a synchronized fashion.
In a typical conventional PLL, a control signal (VC) is provided to a VCO, which then generates an output signal having a frequency corresponding to the control signal. The control signal is generated by feeding both the VCO output signal (or a frequency-divided version of this signal) and a reference signal to a phase and frequency detector. The phase and frequency detector detects differences between the reference signal and VCO output signal and generates two control signals (UP and DN) that are provided to a charge pump. Based on the UP and DN control signals, the charge pump generates an output signal that is then low-pass filtered to produce the VCO control signal, VC.
It is useful for circuit designers to be able to test the operation of the PLL in order to determine whether the PLL and the circuitry that operates in dependence on the PLL output signal will operate properly. In particular, it is helpful to be able to test the operation of the VCO. Conventionally, it is only possible to test the minimum and maximum frequencies that can be generated by the VCO. This is typically accomplished by providing a test signal to the phase and frequency detector. The test signal can be set to cause the phase and frequency detector to alternately operate in three modes: normal operation; VCO high frequency test; and VCO low frequency test. In the high-frequency test mode, the phase and frequency detector asserts only the UP control signal to the charge pump, causing it to generate the maximum output voltage, which in turn drives the VCO to generate its maximum output frequency. In the low-frequency test mode, the phase and frequency detector asserts only the DN control signal to the charge pump, causing it to generate its minimum output voltage, which in turn drives the VCO to generate its minimum output frequency.
It would be desirable to be able to test more than just the minimum and maximum output frequencies of the VCO, however. For instance, the frequency response of a VCO typically is not linear, so it would be useful to be able to test the VCO output frequency with respect to several different voltages of the VCO's input control signal, rather than only the minimum and maximum values.